The subject matter of this disclosure is generally related to transfer of data over a serial chip-to-chip communications link, for example to combine low latency data traffic with high bandwidth data traffic over the serial chip-to-chip communications link.
A Serializer/Deserializer (SerDes) link, also referred to as a serial communications link, includes a pair of functional modules commonly used in high speed communications to compensate for limited input/output pins between chips. These functional modules convert data between serial data and parallel interfaces in each direction. A packet of data that is transmitted through the serial communications link includes overhead and a data payload. The overhead includes a start and end symbol to identify the packet, and a cyclic redundancy code (CRC) value that is used to check the integrity of the transmitted packet.
A low latency (LL) virtual channel and one or more bandwidth (BW) virtual channels can be established through the serial communications link. In this manner, multiple packets are transmitted through a BW virtual channel without interruption. When a particular packet is received to be immediately transmitted through the serial communications link, the particular packet is prepared for transmission on the LL virtual channel. However, the particular packet needs to wait until transmission through the BW virtual channel of a current packet ends. This increases the latency of transmissions through the LL virtual channel. Once the transmission through the BW virtual channel of a current packet ends, the particular packet is transmitted through the LL virtual channel. When the transmission through the LL virtual channel of the particular packet ends, transmission of the multiple packets through the BW virtual channel resumes with a subsequent one from the multiple packets.